It contains 32 receive buffers, each one with its own message filter, and 32 transmit buffers with prioritized arbitration scheme. For optimal support of Higher Layer Protocols (HLP) such as DeviceNet or SDC, the message filter covers the first two data bytes as well.

The design is written in technology independent HDL and can be mapped to ASIC and FPGA architectures and makes use of on-chip SRAM structures. An AMBA 3 Advanced Peripheral Bus (APB) interface enables smooth integration into ARM based SOC’s. This full synchronous bus interface can easily be connect to other system buses.

• Full CAN 2.0A/B compliant
• Conforms to ISO 11898-1
• Tested according to ISO 16845
• Maximum baudrate of 1 Mbps with 8 MHz system clock

• 32 receive buffers
• Each buffer has its own message filter
• Message filter covers: ID, IDE, RTR, Data byte 1 and Data byte 2
• Message buffers can be linked together to build a bigger message array
• Automatic remote transmission request (RTR) response handler with optional generation of RTR interrupt

• 32 Tx message holding registers with programmable priority arbitration
• Message abort command
• Single-shot transmission (no automatic retransmission upon error or arbitration loss)

• AMBA 3 Advanced Peripheral Bus (APB) Interface
• Optional: AMBA Advanced High-performance (AHB) Interface
• Full synchronous zero wait-states interface
• Status and configuration interface

• Local interrupt controller covering message and CAN error sources

• Listen only mode
• Internal loopback mode
• External loopback mode
• SRAM test mode
• Error capture register
  Provides option to either
• show current bit position within CAN message
• show bit position and type of last captured CAN error

• Optimized for low gate-count implementation
• Single port, synchronous memory based
• 100% Synchronous Design

• Verilog RTL source code
• Verification testbench
• Simulation and synthesis scripts
• User guide
• Low-level driver code in c
• Support by email, phone, and fax