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VME Master Controller Core

This core is obsolete and not recommended for new designs. Please use the VME System Controller core VMESCmodule instead.

The VME64M core is a VME compliant master controller for use in FPGA and ASIC based implementations. It is designed to provide master capabilities to VME cards where increased data throughput or added features are required, that can't be provided by the VME64S slave core.
The VME master implementation is fully compliant to the VME specification supporting A16/24/32 addressing modes and D8(EO), D16, D32, D32-BLT, and D64-MBLT data modes. The core contains an interrupter as well as a bus requester.

Block Diagram

Features

Master Interface
  • Addressing modes: A16, A24, A32
  • Data modes: D8(EO), D16, D32, D32-BLT, D64-MBLT
  • Supports data read-ahead and posted write to increase throughout
  • Constant local bus address for DMA transfers to/from FIFOs
Slave Interface
  • Addressing modes: A16, A24, A32
  • Data types: D8(EO), D16, D32, D32-BLT, D64-MBLT
  • Access modes: Read, write, read-modify-write
  • Selectable rescinding DTACK
  • Provides big-endian to little-endian conversion option
Interrupter
  • D8(O), D16, D32
  • Supports RORA and ROAK interrupt schemes
Bus Requester
  • Supports RWD (release when done) and ROR (release on request) arbitration schemes
  • FAIR requester
  • Supports early withdrawal of bus request
Local Bus Interface
  • Fully synchronous bus interface for user logic
  • User selectable wait-states
  • Optional big-endian to little-endian conversion

Documentation

      VME64m master controller datasheet
      VME64m optimized for Actel FPGAs [Product brief]