Inicore Inc.

CANmodule-IIx

FIFO based CAN Controller

CANmodule-IIx is a full functional CAN controller module that contains advanced message filtering, and receive-, and transmit buffers. It is designed to provide a low gate-count CAN interface for FPGA and ASIC based system-on-chip (SOC) integrations.

Full message filtering together with a transmit FIFO and a high priority transmit message buffer support a wide range of applications. An AMBA Advanced Peripheral Bus (APB) interface enables smooth integration into ARM based SOC’s.

Block Diagram

Features

Standard Compliant

• Full CAN 2.0A/B compliant
• ISO 11898-1 compatible
• Supports standard CAN baud rates including 1 Mbps

Receive Path

• 3 fully programmable message filters
• Each message filter covers: ID, IDE, RTR, data byte 1 and data byte 2
• 32 messages deep receive FIFO
• FIFO status indicator
• Message received time-stamp

Transmit Path

• 16 messages deep transmit FIFO
• 1 message buffer for high priority messages to bypass transmit FIFO
• Message Arbiter

System Bus Interface

• AMBA 2.0 Advanced Peripheral Bus Interface
• Other bus interfaces available upon request
• 8-bit, 16-bit, or 32-bit wide data path
• Status and configuration interface

Programmable Interrupt Controller

• Local interrupt controller covering message and CAN error sources

Target for FPGA Implementations

• Supports FPGA systems with two clock domains
• System clock (fast clock)
• CAN clock (slow clock, multiple of 8MHz)

Test and Debug Support

• Listen only mode
• Internal loopback mode
• External loopback mode

SRAM Based Message Buffers

• Optimized for low gate-count implementation
• 100% Synchronous Design

Implementation Options

The core can be configured for your application to get a gate-count optimized implementation:

• Configurations readback enable
• Separate clock domains for CAN and system clock
• Fixed CAN configuration
• Selectable number of message filters: 0, 1, 2, or 3
• Data bus width: 8, 16, or 32-bit