VME Slave Core

This VME64 slave controller is designed for custom integration using standard FPGA and ASIC technologies. It is fully compliant to the VME specification supporting A16/A24/A32 address mode, D8/D16/D32 data modes (read/write/read-modify-write), D16-BLT, D32-BLT, D64-MBLT, as well as interrupt acknowledge cycles. VMEbus timing is guaranteed by using a system clock of 40 MHz or higher. A synchronous design approach is used to simplify inter- facing to the asynchronous VMEbus. The user side interface is full synchronous. Data access is either single cycle or multi-cycle controlled through user wait states.

To support VME slave controller implementations that do not require the full 32-bit address and data bus width, different top-levels are available. Features such as BLT and MBLT can individually be selected to achieve gate-count optimized implementations.

Block Diagram

Block Diagram


  • Data modes: D8, D16, D16-BLT, D32, D32-BLT, D64-MBLT
  • Address modes: A16, A24, A32
  • Access modes: Read, write, read-modify-write
  • Selectable rescinding DTACK
  • Configurable D8, D16, or D32 interrupter
  • Selectable little/big endian conversion
  • Full synchronous user side interface for registers, peripherals, and memories
  • User selectable wait-states

Implementation Options

Several different top-level modules are provided to support gate-count optimized implementations. Following table shows the supported feature set of each module.

Implementation Options


  • VME Slave


VME64s data sheet

Utilization Numbers

Please contact us for utilization number.